I extracted a CoreTemp-Dump.txt from the T6400 CPU.
It's MSR 0xEE flag evalutes to 1:
eax : 0xC6B90400
=> eax & 0x40000000 == true
Which makes CoreTemp assume TjMax == 90°C.
The 0xEE flag was discovered by Rudolf Marek (
click), which you collaborate with on a regular basis and as far as I know is the ONLY person who ever reverse engineered this code. The everest authors also consumed the MSR 0xEE (4th posting:
click).
I e-mailed with Rudolf this weekend that his coretmp.c driver doesn't support Penryn CPUs the correct way. Meanwhile I think he got in touch with you and released an updated driver on Monday:
http://lists.lm-sensors.org/pipermail/l ... 26265.html
I see that you and Rudolf as well extrapolate MSR 0xEE Tj_max reporting to Penryn architectures. Is there any evidence that this is true? I haven't seen any intel documentation regarding this (and do know the CPU spec, the Architecture spec, the IDF SF08, Taipei 08 documentation). Did somebody actually reverse engineer code or have documentation regarding this matter?
The way I see it: If the above intel documentation (processorfinder) is right (T6400 Tj_max = 105°C) , then CoreTemp is worng (TJ_max = 90°C).
Unfortuantely I don't own the T6400. But since the difference between 90 and 105 is 15°C I would expect to easily verify that at idle temps (I know DTS is not calibrated for idle temps, but should be sufficient). I will ask somebody to report his idle temps. If they are around 35-40°C, then CoreTemps assumption of 90°C is likely to be correct.
Any suggestions?