What Determines Core Temp Readout Color Change breakpoints?

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CoreTemp-User279
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What Determines Core Temp Readout Color Change breakpoints?

Post by CoreTemp-User279 »

When the color changes on the core temp readouts, how are the breakpoints determined? Is this the same on all setups or does the program take the CPU ID into account when changeing the readout color? In either case is there a listing of these color change points available? I would hate to try and run the temp up on purpose just to see when it goes red.
Thanks.

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The Coolest
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Post by The Coolest »

What CPU are you running?

Core Temp color codes the temperature differently for each CPU vendor.
In the case of Intel Black/Default means the temp is normal.
Orange means hot, it relies on an offset value kept in the CPU's register.
Red means critical. Critical is when the temperature is within 5C from TjMax value.
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Core Temp - Accurate temperature monitor for Intel's Core/Core 2 and AMD64 processors

CoreTemp-User279
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What Determines Core Temp Readout Color Change breakpoints?

Post by CoreTemp-User279 »

Thanks for the Info. I figured it should depend on the chip. Here's the data on the CPU.

Cores: 2 (Max 2)
Threads: 2 (Max 2)
Processor name: Mobile AMD Turion 64 X2 TL-62 (Tyler)
Processor name string: AMD Turion(tm) 64 X2 Mobile Technology TL-62
Platform: Socket S1g1 (638 pin)
Processor signature: 0x60F82
Processor revision: BH-G2
Process node: 65 nm
Brand ID: 2
Model: 33
Package type: 0x0
Power Limit: 0xC

Processor speed: 2109.48MHz (200.90 x 10.5)
Bus speed: 803.61MHz
Bus ratio: x4
Default speed: 2100.00MHz
Multiplier range: x4.0 - x10.5
Maximum voltage: 1.1750V
Instruction set: MMX+, 3DNow+, 3DNow Prefetch, SSE, SSE2, SSE3, x86-64
Feature set: XD, CnQ
L1 data cache: 2 x 64 KiB, 2-way set associative, 64-byte line size - 1 thread(s)
L1 instruction cache: 2 x 64 KiB, 2-way set associative, 64-byte line size - 1 thread(s)
L2 cache: 2 x 512 KiB, 16-way set associative, 64-byte line size - 1 thread(s)

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